Design and implementation of algorithm and hardware for computing precalculation constant of Montgomery's method

Abstract

The objective of this project is to design a dedicated hardware for smart card equipped with RSA crypto engine, which can generate a precalculation constant for RSA calculation with Montgomery's Method implemented. Montgomery's Method is used for fast RSA calculation, with this Montgomery's precalculation constant generator, it can provide a fast and flexible for RSA crypto smart card. In this project, Altera UP2 Development Kit was used for digital IC design. This development kit has a Altera Flex 10K Field Programmable Gate Arrays (FPGA) which can simulating the hardware environment with Look Up Table (LUT). It consists of Embedded Array Block for memories and Logic Array Block for logical operation. The Input was hardcoded with the core module, and the output can be probed by connecting the chip output pin with signal analyzer, also a dedicated VGA module was developed for display the input and the result. To design the digital IC, Verilog HDL was used. By using the Max Plus II 10.1 design program, it can compile the Verilog coding, doing simulation, also do synthesis on FPGA chips. Verilog HDL has a C/JAVA, like syntax, so the designed algorithm can be easily implemented. The user can design the hardware in three different levels: structural (gate) level, Register Transfer Level (RTL) and full behavioral level. It can provide different level of control and tuning to the hardware design. This product can be widely used in the crypto smart card for Public Key Infrastructure (PKI) using RSA algorithm, or mobile Public Key Infrastructure (Mobile PKI) using ECC algorithm. With applying Montgomery's Method in RSA and ECC calculation, and with this Montgomery's Pre-calculation Constant Module, user can experienced fast, flexible, and more secure PKI and Mobile PKI system, with wide range of security application.