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Title: The investigation of near field couplings between circuit elements on dielectric boards
Other Titles: Jie zhi ban shang zhi dian zi yuan jian ou he zhi yan jiu
Authors: Kwok, Sai Kit (郭世傑)
Department: Dept. of Electronic Engineering
Degree: Doctor of Philosophy
Issue Date: 2005
Publisher: City University of Hong Kong
Subjects: Dielectric devices
Notes: CityU Call Number: TK7872.D53 K85 2005
Includes bibliographical references (leaves 115-128)
Thesis (Ph.D.)--City University of Hong Kong, 2005
vii, 136 leaves : ill. ; 30 cm.
Type: Thesis
Abstract: This research is to investigate the near field couplings between circuit elements on dielectric boards, multilayer LTCCs or in a dielectric packaging box of an integrated circuit. CAD formulae of numerous structures have been derived by using the “parallel plate capacitance” formula and “root of area capacitance” formula. The formulae include the microstrip line, surface printed resistor, strip sitting on top of a two-dimensional integrated circuit (IC) packaging box, strip at a short distance from a two-dimensional integrated circuit (IC) packaging box and a patch with dielectric post. The basic aim is to reduce the field matrices, due to components and integrated circuit packaging on dielectric boards, into CAD formulae to achieve fast computation. The synthetic asymptote and properties in fundamental theory, such as duality, are used in the analysis. By virtue of synthetic asymptote and the properties, physical insights are provided. The average errors of the formulae can frequently be reduced substantially by using only one arbitrary constant. The formulae are verified by the numerical method including the moment method and the commercial software Maxwell. The average errors are found to be no more than 4% in general. In addition to the topics mentioned in the last paragraph, the near field coupling due to IC packaging is also investigated. Usually components are interconnected to an IC. In practice, an IC does not just lie on its dielectric substrate and isolated, instead it is near to some other dielectric objects. The object may be a packaging box enclosing the IC for a simple one layer circuit, or the object may be a nearby packaging box (on top of which the IC of concern lies) in a multilayer circuit, or simply dielectric posts separating the multilayer circuits, e.g., a patch from the ground. When the dielectric object such as a dielectric post or a nearby dielectric casing is small or far away from the IC, a CAD formula of synthetic asymptote has been derived due to the additional capacitance. In the case that the dielectric object is actually a packaging box surrounding the IC of concern with arbitrarily located input and output terminals, a simple synthetic asymptote formula is not possible. In such circumstance, a matrix reduced in size by a novel combination of finite difference (FD) method and moment method (MoM) has been developed. This matrix reduction for fast computation has been given. By using the developed method, the computation time is found to be 10,000 times faster than the commercial software Maxwell.
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