An effective model of cache coherence protocol with VHDL simulation

Wong, Pak Shing (黃柏誠)

Please use this identifier to cite or link to this item: http://dspace.cityu.edu.hk/handle/2031/5294

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DC Field	Value	Language
dc.contributor.author	Wong, Pak Shing (黃柏誠)	en_US
dc.date.accessioned	2008-12-10T01:23:48Z
dc.date.accessioned	2017-09-19T08:28:38Z
dc.date.accessioned	2019-01-22T03:47:37Z	-
dc.date.available	2008-12-10T01:23:48Z
dc.date.available	2017-09-19T08:28:38Z
dc.date.available	2019-01-22T03:47:37Z	-
dc.date.issued	2008	en_US
dc.identifier.other	2008eewps094	en_US
dc.identifier.other	ee2008-4281-wps094 (OAPS)
dc.identifier.uri	http://144.214.8.231/handle/2031/5294	-
dc.description	Nominated as OAPS (Outstanding Academic Papers by Students) paper by Department in 2008-09.
dc.description.abstract	Multiprocessing is an increasingly important area in computer industry. It is an excellent way to build more powerful computers by connecting existing weaker processors together. In multiprocessor environment, processors should work parallel so as to fully utilize their power. However, a problem known as the cache coherence problem is introduced. This report outlines a project which simulates an effective cache coherence protocol with VHDL.	en_US
dc.rights	This work is protected by copyright. Reproduction or distribution of the work in any format is prohibited without written permission of the copyright owner.	en_US
dc.rights	Access is unrestricted.	en_US
dc.subject	Multiprocessors
dc.subject	Cache memory
dc.subject	VHDL (Computer hardware description language)
dc.title	An effective model of cache coherence protocol with VHDL simulation	en_US
dc.contributor.department	Department of Electronic Engineering	en_US
dc.description.supervisor	Supervisor: Dr. Fong, Anthony
Appears in Collections:	Electrical Engineering - Undergraduate Final Year Projects OAPS - Dept. of Electrical Engineering

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