High-speed sense amplifier for SRAM application

Abstract

As the capacity of SRAM entering giga scale range, the performance and reliability of its sense amplifier becomes a challenging issue because of the significant increase in the bit-line and data-line capacitances of the memory blocks. The objective of this project is to design a high-sensitivity, low-power consumption, and high-speed sense amplifier. Op Amp (abbreviated from Operational Amplifier) has been used to amplify ultra-small signal in analog application. The Op Amp structure, with proper modification, can be used for signal sensing application in giga scale memory. This work explores the potential of using CMOS Op Amp in SRAM applications. A high-performance CMOS Op Amp, based on 0.18 µm technology, is designed and simulated with SPICE.