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|Title:||Development of SPICE circuit model for RF CMOS transistor|
|Authors:||Siu, Sik Lam|
|Department:||Department of Electronic Engineering|
|Supervisor:||Supervisor: Dr. Wong, Hei ; Assessor: Prof. Chiang, K S|
|Abstract:||As the continuous downsizing of MOS transistor to deep submicron range, the transis-tor can achieve shorter channel length. The application of CMOS technology in ra-dio-frequency circuit became popular used in recent years because of low production cost, low power consumption and higher integration. This project aims to develop a compact SPICE circuit model for nanoscale CMOS transistor operated at radio fre-quency. The results will be applied in radio-frequency integrated-circuit (RFIC) de-sign. Based on the physical model derived analytically, the intrinsic capacitance, channel resistance, and gate resistance were determined from the s-parameters measured on RFMOS transistors with channel length 90nm, 100nm and 110nm at different num-bers of gate-fingers. Good agreement between simulated circuit model and experimental data was obtained for transistors operated at frequency ranging 9.5GHz to 40GHz and gate bias in the range of -1.5V to 0.75V.|
|Appears in Collections:||Electronic Engineering - Undergraduate Final Year Projects |
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