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|Title: ||A FPGA based image processing module I|
|Authors: ||So, Kai Hong|
|Department: ||Department of Electronic Engineering|
|Issue Date: ||2009|
|Supervisor: ||Supervisor: Dr. Tsang, Peter W M., Assessor: Prof. Yan, Hong|
|Abstract: ||The goal of the task 1 of the project is to implement the adaptive decimation encoder
on Xilinx Virtex II Pro FPGA. It is required that the transmission of the image is low-bit rate
and the compression rate is high. Also, It is required that the encoder is real time operation. It
is most important that logic gate should be as small as possible. In order to achieve the
requirement of the image processing, the technique of the Adaptive decimation scheme can
be applied. The scheme can be applied to the low cost of video production such as Integration
of RFID and Video surveillance.
The goal of the task 2 of the project is to implement Hardware basic blocks (ADC),
(SRAM) and (SRAM Control). This basic block can be provided for further use. For
example, the scrambling core would be implemented by these basic blocks.
In this project, we would design two tasks to implement image processing based on FPGA.
Task A is Adaptive Decimation Encoder detailed in Part I of the report. Task B is hardware
implementation to build basic block detailed in Part II of the report.|
|Appears in Collections:||Electronic Engineering - Undergraduate Final Year Projects|
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