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Title:  Study of injectionlocked frequency dividers for microwave and millimeterwave communication applications 
Other Titles:  Ying yong yu wei bo yu hao mi bo tong xin de zhu ru suo ding fen pin qi de yan jiu 應用於微波與毫米波通信的注入鎖定分頻器的研究 
Authors:  Li, Jialin (李家林) 
Department:  Department of Electronic Engineering 
Degree:  Doctor of Philosophy 
Issue Date:  2009 
Publisher:  City University of Hong Kong 
Subjects:  Frequency dividers. Microwave communication systems. 
Notes:  CityU Call Number: TK6565.F7 L5 2009 xix, 187 leaves : ill. 30 cm. Thesis (Ph.D.)City University of Hong Kong, 2008. Includes bibliographical references (leaves 166182) 
Type:  thesis 
Abstract:  This thesis presents some key issues and novel locking schemes to design the
injectionlocked frequency dividers. First, a general locking equation is derived that
can be applied not only to the subharmonic and superharmonic injectionlocking,
but also to the fundamental and mixed injectionlocking. The mixed injectionlocking
or called as fractional frequency division is defined as R = ωin /ωout = M/N, where ωin
and ωout are input and output frequencies, respectively, while M and N are integers
and bigger than one. It is an important locking scheme in modern wireless
reconfigurable multifunction or multiservice communications systems, because the
use of fractionalorder frequency dividers in a transmitterreceiver system would
enable reducing the number of synchronized oscillators or phase locked loops (PLLs),
resulting in a low cost and compact system integration. Hence, the thesis is primarily
focused on this kind of locking scheme.
Second, techniques to enhance the harmonic power level or nonlinearity of an
active device are analytically studied and experimentally validated with good
agreement. It is believed that the derived harmonic enhancement techniques can be
widely utilized in the microwave and millimeterwave nonlinear circuits, such as subharmonic
injectionlocking, superharmonic injectionlocking, frequency multiplying,
frequency mixing, harmonic oscillated oscillator, and so on.
Third, an important phenomenon in the injectionlocked frequency divider, namely iithe
locking process, is theoretically derived and experimentally investigated for both
fractional and integral division ratios of the developed frequency dividers.
The thesis presents five frequency divider demonstrators, called as circuits I, II, III,
IV and V. The first four circuits are fractional division ratios, while the circuit V is a
Kaband integral division frequency divider that features a high division ratio (up to 9
using only one transistor) and low dc power dissipation.
Circuit I is called as transmissiontype injection locking. The studies indicate that
with proper bias condition and optimally determining the reflector, the desired
harmonic power levels at the input port of the frequency divider can be enhanced. The
results show that the achieved locking ranges are 407, 201, 147, and 85 MHz for
frequency division ratios R = ωin /ωout = 1.5, 2.5, 3.5 and 4.5, respectively. The studies
also indicate that the locking range is associated with the Q factor of the tuning circuit
of the divider, and is further related to the reverse bias condition of the varactor. A
lower bias corresponds to a lower Q value, thus leading to a wider locking range. On
the other hand, the noise performance of the developed frequency divider for different
division ratios is also analyzed. The locking process in the injectionlocked frequency
divider is derived, and experimental demonstration on a division ratio R = 1.5 is
performed.
Circuit II employs the reflectiontype injection locking. The use of reflectiontype
injection locking is due to the fact that the desired harmonic power level at the
collector of a bipolar junction transistor is higher than that of the base, thus resulting
in the locking range enhancement or, equivalently, reducing the dc power dissipation.
Meanwhile, the reflector studied in circuit I is replaced with a lowpass filtering
network, which is implemented based on a novel compact microstrip resonator. On
the other hand, loading effects are considered in this circuit design. The input loading
effect is minimized with the use of a highpass filtering network that is based on the
halfmode substrate integrated waveguide, while the output loading effect is reduced
by employing a buffer amplifier. Demonstrations on the implemented frequency
divider for a division ratio R = 4.5 indicate that the achieved locking ranges are 297
and 451 MHz, respectively, under low dc power dissipations of 8.6 and 12 mW. The iiinoise
performance of this frequency divider is also investigated.
A new locking scheme is studied and utilized to design a fractional frequency
divider (circuit III). The divider consists of a highpass filtering network that is also
based on the halfmode substrate integrated waveguide, an modified Colpitts
oscillator, a wideband bandpass filter with sharp rolloff and broadband suppression,
and a buffer amplifier. The bandpass filter is evolved from the parallelcoupled
resonator, where the size reduction is implemented using an Sshaped resonator, and
the wideband suppression is achieved with the help of the compact microstrip
resonator. Demonstrations on the studied divider circuit for the division ratio R = 4.5
indicate that a locking range of 1007 MHz is observed, while the divider consumes a
low dc power of 10.2 mW. The phasenoise model and noise performance of this
frequency divider is studied and discussed.
The locking scheme for circuit IV presents a new concept to flexibly design the
injectionlocked fractional frequency divider. The requirement to implement such a
locking scheme is that the index N can be decomposed into N1 × N2, where both N1
and N2 are integral and bigger than one. Hence, the division ratio R = M/N becomes R
= M/(N1 × N2). The concept is implemented by using a frequency divider circuit with
a division ratio R = M/N = 7/6. Demonstration on the fabricated frequency divider
illustrates that a locking range of 287 MHz is observed, while it consumes a low
current of 7.9 mA with a dc power dissipation of 8.4 mW.
The circuit V is a Kaband integral division frequency divider, which is composed
of a bandpass filtering network with the center frequency of 27 GHz, a modified
Colpitts oscillator with a fundamental oscillation frequency of 3.0 GHz, and a lowpass
filtering network. The developed bandpass filter is a dualmode loop resonator
filter with inline feedlines, while the lowpass filter is based on the compact
microstrip resonator. The studied frequency divider performs a 27to3 GHz
frequency conversion, corresponding to a division ratio R = 9. The locking process in
this frequency divider is analyzed and experimentally demonstrated. Performance
including locking range and phase noise of the developed divider is also investigated.
With 27to3 GHz frequency conversions, the proposed frequency divider achieves ivthe
locking ranges of 241 and 340 MHz, respectively, under low dc power
consumptions of 10 and 26.6 mW.
One of the practical applications utilizing the developed frequency divider
incorporated into a low cost PLL to stabilize a high frequency oscillator is studied and
designed. A frequency divider with high division ratio and simple architecture is
inserted between a Kband oscillator and a PLL, in which the frequency divider
converts the high frequency to a lower one that enables the PLL to properly work.
Formulation of such a high frequency oscillator system is performed and experimental
performance is presented and analyzed.
With abovementioned performances and advantages, it is believed that the studied
frequency divider circuits are attractive for further development toward practical
applications in the modern microwave and millimeterwave wireless communications
systems. 
Online Catalog Link:  http://lib.cityu.edu.hk/record=b2374876 
Appears in Collections:  EE  Doctor of Philosophy

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