Study of injection-locked frequency dividers for microwave and millimeter-wave communication applications

Abstract

This thesis presents some key issues and novel locking schemes to design the injection-locked frequency dividers. First, a general locking equation is derived that can be applied not only to the sub-harmonic and super-harmonic injection-locking, but also to the fundamental and mixed injection-locking. The mixed injection-locking or called as fractional frequency division is defined as R = ωin /ωout = M/N, where ωin and ωout are input and output frequencies, respectively, while M and N are integers and bigger than one. It is an important locking scheme in modern wireless re-configurable multi-function or multi-service communications systems, because the use of fractional-order frequency dividers in a transmitter-receiver system would enable reducing the number of synchronized oscillators or phase locked loops (PLLs), resulting in a low cost and compact system integration. Hence, the thesis is primarily focused on this kind of locking scheme. Second, techniques to enhance the harmonic power level or nonlinearity of an active device are analytically studied and experimentally validated with good agreement. It is believed that the derived harmonic enhancement techniques can be widely utilized in the microwave and millimeter-wave nonlinear circuits, such as subharmonic injection-locking, super-harmonic injection-locking, frequency multiplying, frequency mixing, harmonic oscillated oscillator, and so on. Third, an important phenomenon in the injection-locked frequency divider, namely iithe locking process, is theoretically derived and experimentally investigated for both fractional and integral division ratios of the developed frequency dividers. The thesis presents five frequency divider demonstrators, called as circuits I, II, III, IV and V. The first four circuits are fractional division ratios, while the circuit V is a Ka-band integral division frequency divider that features a high division ratio (up to 9 using only one transistor) and low dc power dissipation. Circuit I is called as transmission-type injection locking. The studies indicate that with proper bias condition and optimally determining the reflector, the desired harmonic power levels at the input port of the frequency divider can be enhanced. The results show that the achieved locking ranges are 407, 201, 147, and 85 MHz for frequency division ratios R = ωin /ωout = 1.5, 2.5, 3.5 and 4.5, respectively. The studies also indicate that the locking range is associated with the Q factor of the tuning circuit of the divider, and is further related to the reverse bias condition of the varactor. A lower bias corresponds to a lower Q value, thus leading to a wider locking range. On the other hand, the noise performance of the developed frequency divider for different division ratios is also analyzed. The locking process in the injection-locked frequency divider is derived, and experimental demonstration on a division ratio R = 1.5 is performed. Circuit II employs the reflection-type injection locking. The use of reflection-type injection locking is due to the fact that the desired harmonic power level at the collector of a bipolar junction transistor is higher than that of the base, thus resulting in the locking range enhancement or, equivalently, reducing the dc power dissipation. Meanwhile, the reflector studied in circuit I is replaced with a low-pass filtering network, which is implemented based on a novel compact microstrip resonator. On the other hand, loading effects are considered in this circuit design. The input loading effect is minimized with the use of a high-pass filtering network that is based on the half-mode substrate integrated waveguide, while the output loading effect is reduced by employing a buffer amplifier. Demonstrations on the implemented frequency divider for a division ratio R = 4.5 indicate that the achieved locking ranges are 297 and 451 MHz, respectively, under low dc power dissipations of 8.6 and 12 mW. The iiinoise performance of this frequency divider is also investigated. A new locking scheme is studied and utilized to design a fractional frequency divider (circuit III). The divider consists of a high-pass filtering network that is also based on the half-mode substrate integrated waveguide, an modified Colpitts oscillator, a wideband band-pass filter with sharp roll-off and broadband suppression, and a buffer amplifier. The band-pass filter is evolved from the parallel-coupled resonator, where the size reduction is implemented using an S-shaped resonator, and the wideband suppression is achieved with the help of the compact microstrip resonator. Demonstrations on the studied divider circuit for the division ratio R = 4.5 indicate that a locking range of 1007 MHz is observed, while the divider consumes a low dc power of 10.2 mW. The phase-noise model and noise performance of this frequency divider is studied and discussed. The locking scheme for circuit IV presents a new concept to flexibly design the injection-locked fractional frequency divider. The requirement to implement such a locking scheme is that the index N can be de-composed into N1 × N2, where both N1 and N2 are integral and bigger than one. Hence, the division ratio R = M/N becomes R = M/(N1 × N2). The concept is implemented by using a frequency divider circuit with a division ratio R = M/N = 7/6. Demonstration on the fabricated frequency divider illustrates that a locking range of 287 MHz is observed, while it consumes a low current of 7.9 mA with a dc power dissipation of 8.4 mW. The circuit V is a Ka-band integral division frequency divider, which is composed of a band-pass filtering network with the center frequency of 27 GHz, a modified Colpitts oscillator with a fundamental oscillation frequency of 3.0 GHz, and a lowpass filtering network. The developed band-pass filter is a dual-mode loop resonator filter with in-line feed-lines, while the low-pass filter is based on the compact microstrip resonator. The studied frequency divider performs a 27-to-3 GHz frequency conversion, corresponding to a division ratio R = 9. The locking process in this frequency divider is analyzed and experimentally demonstrated. Performance including locking range and phase noise of the developed divider is also investigated. With 27-to-3 GHz frequency conversions, the proposed frequency divider achieves ivthe locking ranges of 241 and 340 MHz, respectively, under low dc power consumptions of 10 and 26.6 mW. One of the practical applications utilizing the developed frequency divider incorporated into a low cost PLL to stabilize a high frequency oscillator is studied and designed. A frequency divider with high division ratio and simple architecture is inserted between a K-band oscillator and a PLL, in which the frequency divider converts the high frequency to a lower one that enables the PLL to properly work. Formulation of such a high frequency oscillator system is performed and experimental performance is presented and analyzed. With above-mentioned performances and advantages, it is believed that the studied frequency divider circuits are attractive for further development toward practical applications in the modern microwave and millimeter-wave wireless communications systems.