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|Title:||An object-oriented processor design based on HDL|
|Authors:||Ho, Ka Chung|
|Department:||Department of Electronic Engineering|
|Supervisor:||Supervisor: Dr. Fong, Anthony S S; Assessor: Dr. Wong, K W|
|Abstract:||High Level Instruction Set Computer (HISC) is a computer architecture that uses the operand descriptor to support the Object-Oriented Programming in hardware level. jHISC is a 32-bit processor that implements HISC architecture. In this project, the processer based on the jHISC V4 architecture is pipelined and is implemented in Verilog. The object cache and the object buffer are enhanced, and the branch predictor is added to utilize the pipeline. The performance of the processor is improved compared with the previous version if the required data exists in the object buffer. In fact, the bottleneck still exists between the object buffer and the object cache.|
|Appears in Collections:||Electronic Engineering - Undergraduate Final Year Projects|
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