City University of Hong Kong
DSpace
 

CityU Institutional Repository >
3_CityU Electronic Theses and Dissertations >
ETD - Dept. of Electronic Engineering  >
EE - Doctor of Philosophy  >

Please use this identifier to cite or link to this item: http://hdl.handle.net/2031/6407

Title: A hybrid system co-design with heuristic optimization in dynamic compilation for Java computing
Other Titles: Yi zhong zhen dui Java ji suan de zai dong tai bian yi zhong yun yong qi fa shi you hua de hun he xi tong she ji
一種針對 Java 計算的在動態編譯中運用啟發式優化的混合系統設計
Authors: Yau, Chi Hang (邱致衡)
Department: Department of Electronic Engineering
Degree: Doctor of Philosophy
Issue Date: 2009
Publisher: City University of Hong Kong
Subjects: Compilers (Computer programs)
Java (Computer program language)
Notes: CityU Call Number: QA76.76.C65 Y38 2009
282 leaves : ill. ; 30 cm.
Thesis (Ph.D.)--City University of Hong Kong, 2009.
Includes bibliographical references (leaves 271-282)
Type: Thesis
Abstract: Object-oriented (OO) concept is a widely used paradigm for programming design due to its appealing features, which include encapsulation, inheritance, abstraction, polymorphism and dynamic binding. These features enable produce high quality program codes that are reusable, flexible, maintainable and extendable. After the introduction of Java programming language in mid-90s, object-oriented program further is gaining popularity due to Java’s portability advantages of "write once run anywhere" (WORA) and its dynamic characteristics. These dynamic features include real-time access control checking, array out-of-bound checking, just-in-time or dynamic compilation, automatic garbage collection, object-oriented manipulation, multithreading, dynamic linking-address resolution and distributed programming. However, like most object-oriented languages, Java has the drawback that it requires to be executed in a runtime Java Virtual Machine (JVM) which is to be implemented on top of the underlying architecture to support the features in Java, creating object resolving complexity, accessing overheads, and security vulnerabilities. This research work is to investigate techniques to overcome these bottlenecks. Java processors, such as PicoJava II, have shown to provide significant performance speedup over most of the pure-software JVM. However, since most of the existing Java processors are stack-based engines, instruction level parallelism and other potential execution extensions to boost the speed are limited in such stack architecture. Comparing with other Java processors, our High-level Instruction Set Computing for Java (jHISC) provides the flexibility through the descriptor-based processing to raise instruction level parallelism and further extension techniques to enhance the overall system security and performance. This research puts forward our jHISC processor to two versions: V4.0 and V4.1. It proposes a hybrid system co-design in jHISC with advanced object representation, heuristic optimization in an adaptive dynamic compilation, and advanced instruction folding techniques to enhance the system performance. Our jHISC processor originates hardware support for object-oriented bytecodes and various object manipulations. jHISC V4.0 is targeted for client computing in mobile and embedded market, while jHISC V4.1 is targeted for server computing in workstation and server market. In jHISC V4.0, a baseline compiler is designed to construct our advanced core structure, aiming for an enhanced level instruction parallelism. Through this advanced object representation, our processor can retrieve the field or method’s information and corresponding operand descriptors concurrently. In addition, the access control and array boundary checks are triggered in parallel to verify the relevant modifiers and size information in the descriptors to safeguard the system from malicious attack such as buffer-overflow. However, the overall system performance measured in weighted clock cycles per instruction (CPI) still out-performs significantly other Java chips including PicoJava II’s original format and quick format which do not perform any security checks. There is 93% of bytecodes implemented in hardware directly, of which 83% are object related. The complete system with 4KB instruction cache and 8KB data cache is described by VHDL and implemented in a Virtex FPGA. According to JVM98 benchmark analysis, jHISC V4.0 achieves the lowest weighted clock cycles per instruction (CPI) of 1.75 and 3.88 for overall bytecodes and object-oriented bytecodes respectively. It provides a better CPI performance gain over most other JVMs and Java chips, such as PicoJava II and JOP. Furthermore, the Java bytecodes are folded into jHISC V4.0 instructions dynamically to reduce the redundant stack operations and to incorporate more folding patterns through our efficient instruction folding algorithm. This algorithm is designed in a hardware instruction folding manager with dependency detection and correction unit to further fold dependency patterns. Dynamic (or hotspot) compilation is another main execution technique to enhance the performance of real-time Java execution. The incorporation of dynamic compilation with a Java processor is an innovative design which merges the benefits of both execution techniques in hardware and software to create synergy effect. We propose an adaptive heuristic algorithm to enhance the dynamic compilation, optimizing through an evolutionary heuristic optimization, which are implemented and verified in OpenJDK, a latest open-source Java Virtual Machine released by Sun Microsystems. Two views of benchmark analysis: micro and macro are designed to encounter application-specific optimization and system-specific optimization respectively. The proposed algorithms are standalone tested, and yield 11.1% to 26.6% speedup in micro benchmark analysis and 10.2% speedup in macro benchmark analysis. With these significant speedups, the proposed heuristic is beneficial to integrate into our processor for server computing, and upgrade jHISC to version V4.1. The dynamic compilation control unit for V4.1 is designed to profile and control the dynamic compilation, through our re-engineered architecture and re-designed method invocation mechanisms. Finally, an alternative offline static compilation technique is explored in our system in which a bytecode-to-WHIRL (bc2whirl) module is proposed to interact with the back-end of a promising static compiler called Open64. Comparing with traditional Complex Instruction Set Computing (CISC) and Reduced Instruction Set Computing (RISC), jHISC V4.0 and V4.1 hybrid system together provide better architectures to support object-oriented programs and boost the performance in executing Java, ideal for an advanced Java chip family for embedded, workstation, and server computing.
Online Catalog Link: http://lib.cityu.edu.hk/record=b3947861
Appears in Collections:EE - Doctor of Philosophy

Files in This Item:

File Description SizeFormat
abstract.html134 BHTMLView/Open
fulltext.html134 BHTMLView/Open

Items in CityU IR are protected by copyright, with all rights reserved, unless otherwise indicated.

 

Valid XHTML 1.0!
DSpace Software © 2013 CityU Library - Send feedback to Library Systems
Privacy Policy · Copyright · Disclaimer