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Title: The investigation of RF front end circuits in CMOS technology for ISM band application
Other Titles: Ying yong yu ISM pin duan de CMOS she pin qian duan ji ti dian lu yan jiu
應用於 ISM 頻段的 CMOS 射頻前端積體電路研究
Authors: Xuan, Kai ( 宣凱)
Department: Department of Electronic Engineering
Degree: Doctor of Philosophy
Issue Date: 2011
Publisher: City University of Hong Kong
Subjects: Radio circuits.
Metal oxide semiconductors, Complementary.
Notes: CityU Call Number: TK6550 .X83 2011
v, 116 leaves : ill. 30 cm.
Thesis (Ph.D.)--City University of Hong Kong, 2011.
Includes bibliographical references.
Type: thesis
Abstract: The proliferation of portable communications systems in recent years has resulted in a growing demand for the more aggressive use of CMOS technology to implement compact, low cost, and low power wireless transceivers, where the radio-frequency (RF) front-end circuits act as signal receiving and transmitting, translation and even modulation/de-modulation. In this thesis, several high performance RF-front-end blocks have been implemented with innovations. Firstly, a concurrent dual-band low noise amplifier is implemented, which tries to achieve maximum hardware sharing. With this architecture, the chip area and power consumption will be halved compared to the traditional two-receiver chain architecture. In this work, a fully integrated dual-band (868/915 MHz and 2.4 GHz) low noise amplifier is designed using 0.18-µm CMOS technology for ZigBee applications. By adding the LC tank in the matching networks, the impedance expression is mathematically reconstructed into a quadratic equation, and leads to the dual-band solutions. The gains achieved are over 15 dB in 868/915 MHz and 2.4 GHz and the resulting noise figures are about 2.2 dB and 2.1 dB, respectively. The input and the output reflections achieve -10 dB in both bands. By tuning the varactor in the input and the output LC tanks, the high band operating frequency can be shifted from 1.8 GHz to 2.8 GHz; and the low band operating frequency can be shifted from 600 MHz to 1 GHz. Such topology is convenient for calibrating the frequency drift due to the unexpected parasitics and process variation. The amplifier works at 1.2 V supply voltage with 10 mA current dissipation. The second work is a double balanced Gilbert-cell class-A amplifier bleeding mixer (DBGC CAAB mixer). The injection current is utilized to amplify the local oscillator (LO) signal to improve the performance of the transconductor stage. With this modification, the DBGC CAAB mixer achieves 17.5 dB conversion gain at -14 dBm LO power, and the noise figure is suppressed from 45 dB to 10.7 dB. It is important to stress that the new configuration will not drain additional power compared to the former current bleeding mixers. This topology dramatically relieves the requirement of the LO power. The DBGC CAAB mixer is implemented by 0.18-µm CMOS technology and targets at the 2.4 GHz ISM application with 10 MHz intermediate frequency. The power consumption is 12 mA at 1.5 V supply voltage. The third work in this thesis is a transformer based gate-coupled quadrature VCO (TGC-QVCO). This novel topology avoids the problems in the traditional parallel-coupled quadrature VCO (P-QVCO) and series-coupled quadrature VCO (S-QVCO). As we know, the P-QVCO burns additional power in the parallel coupled transistors and increase the parasitic capacitance at the output node, as a result, decrease the tuning range. The S-QVCO consumes more voltage headroom and reduces the output voltage swing. In this TGC-QVCO, two identical single-phase VCOs are cross-coupled by transformers to the gate of the counterpart-transistors, but don’t consume any more power or reduces the voltage swing. The work is designed by 0.13-µm RFCMOS technology. The centre oscillation frequency is 1.5 GHz, with the tuning range of 18%. The phase noise is -121 dBc/Hz at 1 MHz offset, and the phase error is 0.2°. The oscillator core burns 7 mA current from 1.0 V power supply. Finally, a 2.4 GHz fully integrated CMOS power amplifier based on double-helix transformer is designed, which is implemented by 0.13-µm RFCMOS process. In this transformer design, by using multi-layer and double-helix stacked structure, the transformer features a higher transfer efficiency (84%) and harmonic suppression. The double-helix transformer power amplifier (DHT-PA) is powered by 4 differential pair cascode amplifiers. The proposed DHT-PA delivery 18.2 dBm 1dB compression power and 22.3 dBm saturated power, the PAE are 40.5% and 61%, respectively. Comparing with the lateral transformer based PA, this DHT-PA has a lower high-order harmonics components. The power amplifier works at 3.3 V supply voltage. The resulted chip area is about 1.3 × 0.9 mm2, including the bond pads. At the end of the thesis, author summarizes the work and plans the future works.
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