Study of the gate drive circuit for MOSFET in high power applications

Abstract

This project report presents the relationship between gate drive resistance, parasitic inductance, parasitic capacitance and the MOSFET. How the relationship can be effect the power loss and timing interval during switching period. Thus, an analytical method is applied in entire analysis both turn-on and turn-off transient. This analysis also divided each transient period into several stages. Each stage has corresponding equations such as gate source voltage, drain current and drain source voltage with timing. Finally, through this analysis an optimal gate drive resistance can be obtained based on those equations and the behavior. In this project, a 720W, 400V, 6A open loop buck converter hardware is built for compare with the analytical results. Finally, the result in both practical and theoretical would be well discussed and also a user interface program is built according those theoretical equations. Through this program people would get more familiar with the switching transient behavior with different parameters such stay inductance and capacitance.