Cryptographic Hardware and Secure Processor Design

Abstract

Secure processor has become an essential component of modern information security, is an important way to solve the security threats, risks and vulnerabilities of information systems. A cryptographic-hardware-based secure processor is a trusted platform that can resist malicious attacks from either software or hardware. As a cryptographic primitive, Advanced Encryption Standard (AES) is the most commonly used cryptographic standard in the 21st century, with the advantages of high efficiency, stability and flexibility. This final year project designs a lightweight secure processor model based on a top-down AES Intellectual Property (IP) core design and implementation, and verification on FPGA. Initially, a top-down block diagram of the hardware AES core is proposed based on algorithm research and validation. Then the work is implemented and verified in Register Transfer Level (RTL) design using Verilog Hardware Description Language (HDL), which supports both 128-bit and 256-bit key schemes. Then, the Look-Up Table (LUT) area is further reduced by adopting distributed RAM. Electronic Codebook (ECB) mode and 32-bit pipelined wrapper are adopted in the design. Finally, an AES-128-key version of the design, with 1950 Slice LUTs, 52-cycle-encryption and 80-cycle-computation in the 32-bit pipeline, is adopted as a primitive crypto IP in a secure RISC-V platform on IoT device. Moreover, it also can be instantiated into a RISC-V core PULPino independently and implemented on ZedBoard. The main advantages of this design are low resource utilization, low power consumption and high efficiency.