Synthesis and Characterization of Silicon Nanowires and Silicon Nanowire Based Field Effect Transistor

Abstract

Microelectronic technology has made a big difference in almost every corner of our lives thanks to the progressive development of semiconductor industry. Nowadays, people are making all those electronic devices smaller in size, and better in performance. Yet, challenges also come along since further miniaturization of devices require even better precision technology and the traditional planar fabrication technology will soon feel its confinement. 1D nanostructured materials have brought possibilities to overcome the difficulties and their potential to be applied in the electronic industry has created excitement in a lot of research labs all over the world. In this project, the SiNWs are used for all the experiments. They are synthesized by the Metal-Nanoparticle-Catalyzed-Chemical-Etching method which provides a better alignment of nanowires and easier controllability of its doping concentration as compared to the chemical vapor deposition, laser ablation and thermal evaporation.

In order to measure the conductivity of the as-synthesized SiNWs, they were dispersed onto the silicon wafer randomly. Different masks for lithography were used to fabricate the electrodes. Shadow masking and photolithography defined the size and the pattern of electrode layout. The electrode material to be deposited was also carefully selected since either Schottky contact or ohmic contact would influence the charge flow in the SiNW due to the difference between the work function of the metal and that of the semiconductor. In order to achieve ohmic contact that allows the current flow in either direction, metals with work function higher than the semiconductor was used such as Au.

Once the I-V characteristic of the SiNW was measured, gate voltage applied to the silicon substrate was also examined and the SiNW based field effect transistor was thus constructed (similar to a metal-oxide-semiconductor structure). The transport property of SiNW was manipulated by the application of different gate voltages. Since the SiNW is of p-type, positive gate voltage tends to expel the holes in the nanowire to the negative electrode, thus forming a depletion region with high resistance and a shallow conducting channel. The response of the SiNW FET shows an increase in the conductivity of the SiNW and higher saturation voltage with the negative increase of the gate voltage. Instead of scanning the source-drain voltage, the gate voltage was scanned while keeping the source-drain voltage fixed. The current flow in the source and drain and the corresponding gate voltage applied plotted in either linear or logarithmic scale shed light on the threshold voltage and the depletion threshold voltage of the device.

To improve the performance of SiNW FET, silicon dioxide layer was used to cover the SiNW exposed in ambient environment. The surface was said to be isolated from external environment and the transport properties were observed to change quite a lot. The main mechanism accounting for the increase in hole mobility is the suppression of reaction between the surface and molecular species and reduction of scattering by the surface defects.