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Please use this identifier to cite or link to this item: http://hdl.handle.net/2031/5294

Title: An effective model of cache coherence protocol with VHDL simulation
Authors: Wong, Pak Shing (黃柏誠)
Department: Department of Electronic Engineering
Issue Date: 2008
Supervisor: Supervisor: Dr. Fong, Anthony
Subjects: Multiprocessors
Cache memory
VHDL (Computer hardware description language)
Notes: Nominated as OAPS (Outstanding Academic Papers by Students) paper by Department in 2008-09.
Abstract: Multiprocessing is an increasingly important area in computer industry. It is an excellent way to build more powerful computers by connecting existing weaker processors together. In multiprocessor environment, processors should work parallel so as to fully utilize their power. However, a problem known as the cache coherence problem is introduced. This report outlines a project which simulates an effective cache coherence protocol with VHDL.
Appears in Collections:Electronic Engineering - Undergraduate Final Year Projects
OAPS - Dept. of Electronic Engineering

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